GlobalFoundries VP Details FDX Fusion Technology, Targeting 7nm-Class Performance Without EUV Tools by 2030

GlobalFoundries is pushing the boundaries of semiconductor manufacturing with its newly detailed FDX Fusion technology, an ambitious initiative designed to deliver 7nm-class performance without the astronomical costs and complex supply chain constraints associated with extreme ultraviolet (EUV) lithography tools. During a recent technical briefing, a GlobalFoundries vice president outlined the company’s roadmap for the technology, pointing toward a 2030 target for high-volume manufacturing while relying on traditional planar transistors rather than the finFET or gate-all-around architectures that currently dominate the advanced node landscape.

The semiconductor industry has spent the last decade racing toward smaller transistor nodes, a pursuit that has become inextricably linked to the adoption of EUV lithography. Developed by ASML, EUV machines have become mandatory for producing sub-7nm chips at leading foundries like TSMC, Samsung, and Intel. However, these machines carry price tags exceeding $300 million per unit, creating a massive financial barrier for chip designers and semiconductor fabricters alike. By bypassing EUV requirements entirely, GlobalFoundries is positioning FDX Fusion as an economically viable alternative for applications that require advanced performance tiers without the crushing overhead of cutting-edge lithography equipment.

At the heart of the FDX Fusion strategy is the evolution of Fully Depleted Silicon-on-Insulator technology, a specialty process that GlobalFoundries has championed for years through its 22FDX and similar offerings. FD-SOI platforms have long been recognized for their exceptional energy efficiency, inherent resistance to radiation-induced soft errors, and simplified manufacturing flows compared to bulk silicon alternatives. By advancing this foundational architecture into the FDX Fusion era, the company aims to scale performance metrics up to the 7nm class, opening up new possibilities for automotive, Internet of Things, edge AI, and specialized networking chips that prioritize power efficiency and cost-effectiveness over raw

transistor density.

While achieving 7nm-class performance without EUV is a striking engineering milestone, industry observers note that the approach involves distinct trade-offs. Most notably, FDX Fusion will achieve its performance targets at a relatively low transistor density compared to the hyper-dense, EUV-reliant nodes currently utilized by top-tier foundries for smartphone application processors and high-end graphics cards. Rather than competing directly for the densest possible chip designs, GlobalFoundries is targeting a market sweet spot where performance, power consumption, and wafer cost intersect more favorably for industrial and embedded systems.

The choice to retain planar transistors within the FDX Fusion framework further underscores this pragmatic philosophy. While much of the semiconductor world has transitioned to complex three-dimensional structures—such as FinFETs and, more recently, nanosheet gate-all-around transistors—to maintain electrical control at microscopic scales, planar architectures remain easier and cheaper to manufacture. By refining planar FD-SOI techniques to deliver performance levels traditionally associated with much tighter nodes, GlobalFoundries can sidestep the yield risks and tooling expenses that plague more complex 3D transitions.

The company’s target of 2030 for high-volume manufacturing gives its engineering teams a structured runway to refine the technology, secure ecosystem partnerships, and ensure design enablement tools are ready for commercial adoption. As the semiconductor industry grapples with rising production costs, geopolitical supply chain pressures, and the sheer expense of the post-EUV era, alternatives like GlobalFoundries’ FDX Fusion represent a vital diversification of manufacturing strategies. By offering a path to 7nm-class capabilities using more accessible tools, the company aims to redefine the economics of advanced chip production for the next decade.